1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device, and more specifically, it relates to a nonvolatile semiconductor memory device comprising a MONOS (metal oxide nitride oxide semiconductor) memory cell.
2. Description of the Background Art
A generally known nonvolatile semiconductor memory device comprises a memory cell having a gate structure obtained by stacking a floating gate 20 and a control gate 21, as shown in FIG. 25. This memory cell has a source region 4, a drain region 5 and the aforementioned multilayer gate formed on the main surface of a silicon substrate 1. The floating gate 20 is formed on the main surface of the silicon substrate 1 through an insulator film, and the control gate 21 is formed on the floating gate 20 through an insulator film 22. An insulator film 23 covers the control gate 21 and the floating gate 20.
FIG. 26 shows another conventional nonvolatile semiconductor memory device having a MONOS memory cell, which has been recently proposed.
As shown in FIG. 26, this memory cell has an insulator film (hereinafter referred to as “ONO film”) 6 consisting of a multilayer structure of an oxide film 6a, a nitride film 6b and an oxide film 6c between a gate 7 and a channel. Electrons are injected into or extracted from the nitride film 6b forming the ONO film 6, thereby writing (programming) or erasing data in or from the memory cell. The nitride film 6b is an insulator film, and hence electrons once trapped in the nitride film 6b remain unmoving.
The aforementioned MONOS memory cell has the following advantages: The memory cell can be readily fabricated at a low cost. Two bits/cell can be implemented by trapping electrons on two physically different positions of a single cell. More specifically, electron trap parts R and L can be secured on right and left portions of the nitride film 6b as shown in FIG. 26, for writing data by trapping electrons in the electron trap parts R and L. When the direction of a current fed to the channel is switched in writing and reading, the quantity of change of a threshold voltage is increased with respect to the quantity of electron injection.
Data is written in the MONOS memory cell through channel hot electrons (CHE), and erased through an F-N (Fowler-Nordheim) tunneling phenomenon.
Electrons are injected into the electron trap parts (electron trap regions) R and L provided on the right and left portions of the memory cell shown in FIG. 26, for performing writing. The electrons injected into the electron trap parts R and L remain unmoving in the nitride film 6b, and hence two bits can be written in one cell by inverting source/drain.
In order to erase data, electrons are extracted from the electron trap parts R and L through the F-N tunneling phenomenon. Thus, erasing is performed in units of bits. When performing reading as to each bit and setting a gate voltage to a prescribed value, data of a focused bit can be correctly read regardless of data of the remaining bit. U.S. Pat. No. 6,081,456, for example, discloses a method of applying voltages to respective terminals of the memory cell shown in FIG. 26.
FIG. 27 shows another MONOS memory cell having an islandlike oxide film 24 containing silicon as an electrode trap layer.
The quantity of electrons injected into the floating gate 20 of a conductor in the memory cell shown in FIG. 25 depends on readily controllable factors such as a write voltage, a write time, the thickness of an oxide film etc. In other words, the quantity of electron injection is hardly dispersed in fabrication steps in principle.
In the MONOS memory cell, however, the quantity of electron injection may also depend on the crystal defect level of the nitride film 6b in addition to the aforementioned factors. If the crystal defect level is low, no desired quantity of threshold voltage change can be obtained by increasing the write voltage or the write time.
When a desired quantity of threshold voltage change can be obtained, a threshold voltage distribution margin can be ensured between an erased state (‘1’) and a written state (‘0’), as shown in FIG. 28. When no desired quantity of threshold voltage change can be obtained, however, no threshold voltage distribution margin can be ensured between the erased state (‘1’) and the written state (‘0’) but ‘1’ and ‘0’ may be falsely recognized in any bit as shown in FIG. 29. A product including a bit having such threshold voltage distribution results in reduction of the yield of the product.